rga.h 9.9 KB

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  1. /*
  2. * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
  3. * Authors:
  4. * Zhiqin Wei <wzq@rock-chips.com>
  5. *
  6. * Licensed under the Apache License, Version 2.0 (the "License");
  7. * you may not use this file except in compliance with the License.
  8. * You may obtain a copy of the License at
  9. *
  10. * http://www.apache.org/licenses/LICENSE-2.0
  11. *
  12. * Unless required by applicable law or agreed to in writing, software
  13. * distributed under the License is distributed on an "AS IS" BASIS,
  14. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  15. * See the License for the specific language governing permissions and
  16. * limitations under the License.
  17. */
  18. #ifndef _RGA_DRIVER_H_
  19. #define _RGA_DRIVER_H_
  20. #ifdef __cplusplus
  21. extern "C"
  22. {
  23. #endif
  24. /* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX,
  25. * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */
  26. typedef enum _Rga_SURF_FORMAT {
  27. RK_FORMAT_RGBA_8888 = 0x0 << 8, /* [0:31] R:G:B:A 8:8:8:8 little endian */
  28. RK_FORMAT_RGBX_8888 = 0x1 << 8, /* [0:31] R:G:B:X 8:8:8:8 little endian */
  29. RK_FORMAT_RGB_888 = 0x2 << 8, /* [0:23] R:G:B 8:8:8 little endian */
  30. RK_FORMAT_BGRA_8888 = 0x3 << 8, /* [0:31] B:G:R:A 8:8:8:8 little endian */
  31. RK_FORMAT_RGB_565 = 0x4 << 8, /* [0:15] R:G:B 5:6:5 little endian */
  32. RK_FORMAT_RGBA_5551 = 0x5 << 8, /* [0:15] R:G:B:A 5:5:5:1 little endian */
  33. RK_FORMAT_RGBA_4444 = 0x6 << 8, /* [0:15] R:G:B:A 4:4:4:4 little endian */
  34. RK_FORMAT_BGR_888 = 0x7 << 8, /* [0:23] B:G:R 8:8:8 little endian */
  35. RK_FORMAT_YCbCr_422_SP = 0x8 << 8, /* 2 plane YCbCr little endian
  36. * plane 0: [0:7] Y
  37. * plane 1: 2x1 subsampled [0:15] Cb:Cr 8:8 */
  38. RK_FORMAT_YCbCr_422_P = 0x9 << 8, /* 3 plane YCbCr little endian
  39. * plane 0: [0:7] Y
  40. * plane 1: 2x1 subsampled [0:7] Cb
  41. * plane 2: 2x1 subsampled [0:7] Cr */
  42. RK_FORMAT_YCbCr_420_SP = 0xa << 8, /* 2 plane YCbCr little endian
  43. * plane 0: [0:7] Y
  44. * plane 1: 2x2 subsampled [0:15] Cr:Cb 8:8 */
  45. RK_FORMAT_YCbCr_420_P = 0xb << 8, /* 3 plane YCbCr little endian
  46. * plane 0: [0:7] Y
  47. * plane 1: 2x2 subsampled [0:7] Cb
  48. * plane 2: 2x2 subsampled [0:7] Cr */
  49. RK_FORMAT_YCrCb_422_SP = 0xc << 8, /* 2 plane YCbCr little endian
  50. * plane 0: [0:7] Y
  51. * plane 1: 2x1 subsampled [0:15] Cb:Cr 8:8 */
  52. RK_FORMAT_YCrCb_422_P = 0xd << 8, /* 3 plane YCbCr little endian
  53. * plane 0: [0:7] Y
  54. * plane 1: 2x1 subsampled [0:7] Cr
  55. * plane 2: 2x1 subsampled [0:7] Cb */
  56. RK_FORMAT_YCrCb_420_SP = 0xe << 8, /* 2 plane YCbCr little endian
  57. * plane 0: [0:7] Y
  58. * plane 1: 2x2 subsampled [0:15] Cb:Cr 8:8 */
  59. RK_FORMAT_YCrCb_420_P = 0xf << 8, /* 3 plane YCbCr little endian
  60. * plane 0: [0:7] Y
  61. * plane 1: 2x2 subsampled [0:7] Cr
  62. * plane 2: 2x2 subsampled [0:7] Cb */
  63. RK_FORMAT_BPP1 = 0x10 << 8, /* [0] little endian */
  64. RK_FORMAT_BPP2 = 0x11 << 8, /* [0:1] little endian */
  65. RK_FORMAT_BPP4 = 0x12 << 8, /* [0:3] little endian */
  66. RK_FORMAT_BPP8 = 0x13 << 8, /* [0:7] little endian */
  67. RK_FORMAT_Y4 = 0x14 << 8, /* [0:3] Y little endian */
  68. RK_FORMAT_YCbCr_400 = 0x15 << 8, /* [0:7] Y little endian */
  69. RK_FORMAT_BGRX_8888 = 0x16 << 8, /* [0:31] B:G:R:X 8:8:8:8 little endian */
  70. RK_FORMAT_YVYU_422 = 0x18 << 8, /* [0:31] Y0:Cr0:Y1:cb0 8:8:8:8 little endian */
  71. RK_FORMAT_YVYU_420 = 0x19 << 8, /* ODD : [0:31] Y0:Cr0:Y1:cb0 8:8:8:8 little endian
  72. * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */
  73. RK_FORMAT_VYUY_422 = 0x1a << 8, /* [0:31] Cr0:Y0:Cb0:Y1 8:8:8:8 little endian */
  74. RK_FORMAT_VYUY_420 = 0x1b << 8, /* ODD : [0:31] Cr0:Y0:Cb0:Y1 8:8:8:8 little endian
  75. * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */
  76. RK_FORMAT_YUYV_422 = 0x1c << 8, /* [0:31] Y0:Cb0:Y1:cr0 8:8:8:8 little endian */
  77. RK_FORMAT_YUYV_420 = 0x1d << 8, /* ODD : [0:31] Y0:Cb0:Y1:cr0 8:8:8:8 little endian
  78. * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */
  79. RK_FORMAT_UYVY_422 = 0x1e << 8, /* [0:31] Cb0:Y0:Cr0:Y1 8:8:8:8 little endian */
  80. RK_FORMAT_UYVY_420 = 0x1f << 8, /* ODD : [0:31] Cb0:Y0:Cr0:Y1 8:8:8:8 little endian
  81. * EVEN: [0:31] Y2:Y3:X:X 8:8:8:8 little endian */
  82. RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, /* 2 plane YCbCr little endian
  83. * plane 0: [0:9] Y
  84. * plane 1: 2x2 subsampled [0:19] Cb:Cr 10: 10 (default)
  85. * or
  86. * plane 1: 2x2 subsampled [0:23] Cb:Cr 16: 16 */
  87. RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, /* 2 plane YCbCr little endian
  88. * plane 0: [0:9] Y
  89. * plane 1: 2x2 subsampled [0:19] Cr:Cb 10: 10 (default)
  90. * or
  91. * plane 1: 2x2 subsampled [0:23] Cr:Cb 16: 16 */
  92. RK_FORMAT_YCbCr_422_SP_10B = 0x22 << 8, /* 2 plane YCbCr little endian
  93. * plane 0: [0:9] Y
  94. * plane 1: 2x1 subsampled [0:19] Cb:Cr 10:10 (default)
  95. * or
  96. * plane 1: 2x1 subsampled [0:23] Cb:Cr 16: 16 */
  97. RK_FORMAT_YCrCb_422_SP_10B = 0x23 << 8, /* 2 plane YCbCr little endian
  98. * plane 0: [0:9] Y
  99. * plane 1: 2x1 subsampled [0:19] Cr:Cb 10:10 (default)
  100. * or
  101. * plane 1: 2x1 subsampled [0:23] Cr:Cb 16: 16 */
  102. /* For compatibility with misspellings */
  103. RK_FORMAT_YCbCr_422_10b_SP = RK_FORMAT_YCbCr_422_SP_10B << 8,
  104. RK_FORMAT_YCrCb_422_10b_SP = RK_FORMAT_YCrCb_422_SP_10B << 8,
  105. RK_FORMAT_BGR_565 = 0x24 << 8, /* [0:16] B:G:R 5:6:5 little endian */
  106. RK_FORMAT_BGRA_5551 = 0x25 << 8, /* [0:16] B:G:R:A 5:5:5:1 little endian */
  107. RK_FORMAT_BGRA_4444 = 0x26 << 8, /* [0:16] B:G:R:A 4:4:4:4 little endian */
  108. RK_FORMAT_ARGB_8888 = 0x28 << 8, /* [0:31] A:R:G:B 8:8:8:8 little endian */
  109. RK_FORMAT_XRGB_8888 = 0x29 << 8, /* [0:31] X:R:G:B 8:8:8:8 little endian */
  110. RK_FORMAT_ARGB_5551 = 0x2a << 8, /* [0:16] A:R:G:B 5:5:5:1 little endian */
  111. RK_FORMAT_ARGB_4444 = 0x2b << 8, /* [0:16] A:R:G:B 4:4:4:4 little endian */
  112. RK_FORMAT_ABGR_8888 = 0x2c << 8, /* [0:31] A:B:G:R 8:8:8:8 little endian */
  113. RK_FORMAT_XBGR_8888 = 0x2d << 8, /* [0:31] X:B:G:R 8:8:8:8 little endian */
  114. RK_FORMAT_ABGR_5551 = 0x2e << 8, /* [0:16] A:B:G:R 5:5:5:1 little endian */
  115. RK_FORMAT_ABGR_4444 = 0x2f << 8, /* [0:16] A:B:G:R 4:4:4:4 little endian */
  116. RK_FORMAT_RGBA2BPP = 0x30 << 8, /* [0:1] Color:Alpha 1:1 little endian */
  117. RK_FORMAT_A8 = 0x31 << 8, /* [0:7] Alpha */
  118. RK_FORMAT_YCbCr_444_SP = 0x32 << 8, /* 2 plane YCbCr little endian
  119. * plane 0: [0:7] Y
  120. * plane 1: non-subsampled [0:15] Cb:Cr 8:8 */
  121. RK_FORMAT_YCrCb_444_SP = 0x33 << 8, /* 2 plane YCrCb little endian
  122. * plane 0: [0:7] Y
  123. * plane 1: non-subsampled [0:15] Cr:Cb 8:8 */
  124. RK_FORMAT_Y8 = 0x34 << 8, /* [0:7] zero:Y 4:4 little endian */
  125. RK_FORMAT_UNKNOWN = 0x100 << 8,
  126. } RgaSURF_FORMAT;
  127. enum {
  128. yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
  129. yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
  130. yuv2rgb_mode2 = 0x2, /* BT.709 */
  131. rgb2yuv_601_full = 0x1 << 8,
  132. rgb2yuv_709_full = 0x2 << 8,
  133. yuv2yuv_601_limit_2_709_limit = 0x3 << 8,
  134. yuv2yuv_601_limit_2_709_full = 0x4 << 8,
  135. yuv2yuv_709_limit_2_601_limit = 0x5 << 8,
  136. yuv2yuv_709_limit_2_601_full = 0x6 << 8, //not support
  137. yuv2yuv_601_full_2_709_limit = 0x7 << 8,
  138. yuv2yuv_601_full_2_709_full = 0x8 << 8, //not support
  139. yuv2yuv_709_full_2_601_limit = 0x9 << 8, //not support
  140. yuv2yuv_709_full_2_601_full = 0xa << 8, //not support
  141. rgb2yuv_709_limit = 0xb << 8,
  142. yuv2rgb_709_full = 0xc << 8, //not support
  143. yuv2yuv_601_limit_2_601_full = 0xd << 8, //not support
  144. yuv2yuv_601_full_2_601_limit = 0xe << 8, //not support
  145. yuv2yuv_709_limit_2_709_full = 0xf << 8, //not support
  146. yuv2yuv_709_full_2_709_limit = 0x10 << 8, //not support
  147. full_csc_mask = 0xf00,
  148. };
  149. enum {
  150. RGA3_SCHEDULER_CORE0 = 1 << 0,
  151. RGA3_SCHEDULER_CORE1 = 1 << 1,
  152. RGA2_SCHEDULER_CORE0 = 1 << 2,
  153. RGA2_SCHEDULER_CORE1 = 1 << 3,
  154. RGA_CORE_MASK = 0xf,
  155. RGA_NONE_CORE = 0x0,
  156. };
  157. /* RGA3 rd_mode */
  158. enum
  159. {
  160. raster_mode = 0x1 << 0,
  161. fbc_mode = 0x1 << 1,
  162. tile_mode = 0x1 << 2,
  163. };
  164. #ifdef __cplusplus
  165. }
  166. #endif
  167. #endif /*_RK29_IPP_DRIVER_H_*/